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DATA SHEET
PD75304B,75306B,75308B
4-BIT SINGLE-CHIP MICROCOMPUTER
MOS INTEGRATED CIRCUIT
DESCRIPTION
The PD75308B is a 75X Series 4-bit single-chip microcomputer capable of the same data processing as an 8-bit microcomputer. It is a low voltage operation version of the PD75308 with on-chip LCD controller/driver. Operation at an ultra-low voltage of 2.0 V is possible. An ultra small-sized plastic QFP (12 x 12 mm) is also provided and it is perfect for small-sized set that uses an LCD panel. Functions, etc., are described in detail in the User's Manual. Please be sure to read this manual when carrying out design work. PD75308 User's Manual: IEM-5016
FEATURES * Ultra-low-voltage operation possible: VDD = 2.0 to 6.0 V
* Can be driven by two 1.5 V manganese batteries.
* On-chip memory
* Program memory (ROM) : 8064 x 8 bit (PD75308B) : 6016 x 8 bit (PD75306B) : 4096 x 8 bit (PD75304B) * Data memory (RAM) : 512 x 4 bit * Instruction execution time adjustment function convenient in high-speed operation and power saving * 0.95 s, 1.91 s, 15.3 s (4.19 MHz operation) * 122 s (32.768 kHz operation)
* Built-in programmable LCD controller/driver
* LCD drive voltage: 2.0 V to VDD
* An ultra small-sized plastic QFP (12 x 12 mm) is provided.
* Suitable for small-sized set, such as a camera.
* On-chip PROM products available
* On-chip one-time PROM products : PD75P308, 75P316A * On-chip EPROM products : PD75P308, 75P316B
APPLICATIONS
Remote control, integrated camera type VCR, camera, gas meter, etc. Unless there are any particular functional differences, the PD75308B is described in this document as a representative product.
The information in this document is subject to change without notice.
Document No. IC-2913C (O. D. No. IC-8082D) Date Published January 1994 P Printed in Japan
The mark 5 shows major revised points.
(c) NEC Corporation 1991
PD75304B,75306B,75308B
ORDERING INFORMATION
Ordering Code
Package 80-pin 80-pin 80-pin 80-pin 80-pin 80-pin 80-pin 80-pin 80-pin plastic plastic plastic plastic plastic plastic plastic plastic plastic QFP (s 14 mm) s QFP (14 x 20 mm) TQFP(fine pitch)(s 12 mm) s QFP (s 14 mm) s QFP (14 x 20 mm) TQFP(fine pitch)(s 12 mm)) s QFP (s 14 mm) s QFP (14 x 20 mm) TQFP(fine pitch)(s 12 mm) s
Quality Grade Standard Standard Standard Standard Standard Standard Standard Standard Standard
PD75304BGC-xxx-3B9 PD75304BGF-xxx-3B9 PD75304BGK-xxx-BE9 PD75306BGC-xxx-3B9 PD75306BGF-xxx-3B9 PD75306BGK-xxx-BE9 PD75308BGC-xxx-3B9 PD75308BGF-xxx-3B9 PD75308BGK-xxx-BE9
Remarks
xxx is the ROM code number.
Please refer to "Quality grade on NEC Semiconductor Devices" (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
2
PD75304B,75306B,75308B
FUNCTION OUTLINE (1/2)
Item Number of basic instructions 41
Function
Instruction cycle
0.95 s, 1.91 s, 15.3 s (main system clock: 4.19 MHz operation) 122 s (subsystem clock: 32.768 kHz operation) ROM 8064 x 8 bits (PD75308B), 6016x 8 bits (PD75306B), 4096x 8 bits (PD75304B) 512 x 4 bits * 4-bit manipulation: 8 (B, C, D, E, H, L, X, A) * 8-bit manipulation: 4 (BC, DE, HL, XA) * Bit accumulator (CY) * 4-bit accumulator (A) * 8-bit accumulator (XA) * * * * Various bit manipulation instructions Efficient 4-bit data manipulation instructions 8-bit data transfer instructions GETI instruction that can implement arbitrary 2-byte/3-byte instructions with 1 byte 8 16 CMOS input Pull-up by software possible : 23 CMOS input/output CMOS output N-ch open-drain input/output Used with segment pin 10 V withstand voltage, pull-up by mask option possible : 8 40 8
On-chip memory RAM
General register
Accumulators
Instruction set
I/O lines
8
LCD controller/driver
* Number of segments selection: 24/28/32 segments (4/8 can be switched at bit port output.) * Display mode selection: Static, 1/2 duty, 1/3 duty (1/2 bias), 1/3 duty (1/3 bias), 1/4 duty * LCD drive division resistor can be incorporated by mask option VDD = 2.0 to 6.0 V * 8-bit timer/event counter * Clock source: 4 stages * Event count possible
Supply voltage range
Timer
3 channels
* 8-bit basic interval timer * Standard clock generation: 1.95 ms, 7.82 ms, 31.3 ms, 250 ms (4.19 MHz operation) * Watchdog timer application possible
3
PD75304B,75306B,75308B
FUNCTION OUTLINE (2/2)
Item
Function * Watch timer * 0.5 seconds time interval generation * Count clock source: Main system clock and subsystem clock switchable * Fast watch mode (3.9 ms time interval generation) * Buzzer output possible (2 kHz)
Timer
3 channels
8-bit serial interface
* Three modes application possible * 3-wire serial I/O mode * 2-wire serial I/O mode * SBI mode * LSB top/MSB top switchable Special bit manipulation memory: 16 bits * Perfect for remote control application Timer/event counter output (PTO0): Arbitrary frequency square wave output
Bit sequential buffer
Clock output function
Clock output (PCL): , 524, 262, 65.5 kHz (4.19 MHz operation) Buzzer output (BUZ): 2 kHz (4.19 MHz or 32.768 kHz operation) * External: 3 * Internal: 3 * External: 1 * Internal: 1 * Main system clock oscillation ceramic/crystal oscillation circuit: 4.194304 MHz * Subsystem clock oscillation crystal oscillation circuit: 32.768 kHz STOP/HALT mode * 80-pin plastic QFP (14 x 20 mm) * 80-pin plastic QFP (s 14 mm) s * 80-pin plastic TQFP (fine pitch) (s 12 mm) s
Vectored interrupt
Test input
System clock oscillator
Standby
Package
4
PD75304B,75306B,75308B
CONTENTS 1. PIN CONFIGURATION (TOP VIEW)............................................................................................... 2. BLOCK DIAGRAM............................................................................................................................ 3. PIN FUNCTIONS ..............................................................................................................................
3.1 3.2 3.3 3.4 3.5 PORT PINS .............................................................................................................................................. NON-PORT PINS ..................................................................................................................................... PIN INPUT/OUTPUT CIRCUITS .............................................................................................................. RECOMMENDED CONNECTION OF UNUSED PINS ............................................................................. PRECAUTIONS CONCERNING P00/INT4 PIN AND RESET PIN ...........................................................
6 8 9
9 11 13 15 16
4. 5.
MEMORY CONFIGURATION .......................................................................................................... PERIPHERAL HARDWARE FUNCTIONS ........................................................................................
5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 PORTS ..................................................................................................................................................... CLOCK GENERATOR ............................................................................................................................... CLOCK OUTPUT CIRCUIT ....................................................................................................................... BASIC INTERVAL TIMER ........................................................................................................................ WATCH TIMER ........................................................................................................................................ TIMER/EVENT COUNTER ....................................................................................................................... SERIAL INTERFACE ................................................................................................................................. LCD CONTROLLER/DRIVER .................................................................................................................... BIT SEQUENTIAL BUFFER ......................................................................................................................
16 21
21 22 23 24 25 26 28 30 32
6. 7. 8. 9.
INTERRUPT FUNCTION ................................................................................................................. STANDBY FUNCTION .................................................................................................................... RESET FUNCTION .......................................................................................................................... INSTRUCTION SET .........................................................................................................................
32 34 35 37
10. MASK OPTION SELECTION ............................................................................................................ 45 11. ELECTRICAL SPECIFICATIONS ...................................................................................................... 12. PACKAGE INFORMATION .............................................................................................................. 13. RECOMMENDED SOLDERING CONDITIONS ................................................................................ APPENDIX A. DIFFERENCES AMONG SERIES PRODUCTS .............................................................. APPENDIX B. DEVELOPMENT TOOLS ............................................................................................... APPENDIX C. RELATED DOCUMENTS .............................................................................................. 46 64 67 70 72 73
5
PD75304B,75306B,75308B
1. PIN CONFIGURATION (TOP VIEW)
S1 S0 RESET P73/KR7 P72/KR6 P71/KR5 P70/KR4 P63/KR3 P62/KR2
S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24/BP0 S25/BP1 S26/BP2 S27/BP3 S28/BP4 S29/BP5 S30/BP6 S31/BP7
1 2 3 4 5 6 7 8 9
8079787776 757473 7271 70696867666564636261
P61/KR1
S11 S10
S9 S8 S7
S6 S5 S4 S3 S2
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
P60/KR0 X2 X1 NC XT2 XT1 VDD P33 P32 P31/SYNC P30/LCDCL P23/BUZ P22/PCL P21 P20/PTO0 P13/TI0 P12/INT2 P11/INT1 P10/INT0 P03/SI/SB1
PD75304BGC-xxx-3B9 PD75304BGK-xxx-BE9 PD75306BGC-xxx-3B9 PD75306BGK-xxx-BE9 PD75308BGC-xxx-3B9 PD75308BGK-xxx-BE9
10 11 12 13 14 15 16 17 18 19
20 2122232425 262728 2930 31323334353637383940
6
P50 P51 P52 P53 P00/INT4 P01/SCK P02/SO/SB0
COM0
COM1 COM2
COM3 BIAS VLC0 VLC1 VLC2
P40 P41 P42 P43 VSS
PD75304B,75306B,75308B
S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 RESET P73/KR7 P72/KR6 P71/KR5
S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24/BP0 S25/BP1 S26/BP2 S27/BP3 S28/BP4 S29/BP5 S30/BP6 S31/BP7 COM0 COM1 COM2 COM3
80797877767574737271706968676665 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25262728293031323334353637383940
S11
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
P70/KR4 P63/KR3 P62/KR2 P61/KR1 P60/KR0 X2 X1 NC XT2 XT1 VDD P33 P32 P31/SYNC P30/LCDCL P23/BUZ P22/PCL P21 P20/PTO0 P13/TI0 P12/INT2 P11/INT1 P10/INT0 P03/SI/SB1
P00 to 03 P10 to 13 P20 to 23 P30 to 33 P40 to 43 P50 to 53 P60 to 63 P70 to 73 BP0 to 7 KR0 to 7 SCK SI SO SB0,1 RESET
: : : : : : : : : : : : : : :
Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Bit Port Key Return Serial Clock Serial Input Serial Output Serial Bus 0, 1 Reset Input
VLC0 VLC1 VLC2 P40 P41 P42 P43 VSS P50 P51 P52 P53 P00/INT4 P01/SCK P02/SO/SB0
PD75304BGF-xxx-3B9 PD75306BGF-xxx-3B9 PD75308BGF-xxx-3B9
BIAS
S0 to 31 COM0 to 3 VLC0-2 BIAS LCDCL SYNC TI0 PTO0 BUZ PCL INT0, 1, 4 INT2 X1, 2 XT1, 2 NC
: : : : : : : : : : : : : : :
Segment Output 0 to 31 Common Output 0 to 3 LCD Power Supply 0 to 2 LCD Power Supply Bias Control LCD Clock LCD Synchronization Timer Input 0 Programmable Timer Output 0 Buzzer Clock Programmable Clock External Vectored Interrupt 0, 1, 4 External Test Input 2 Main System Clock Oscillation 1, 2 Subsystem Clock Oscillation 1, 2 No Connection
7
8
BASIC INTERVAL TIMER INTBT TI0/P13 PTO0/P20 TIMER/EVENT COUNTER #0 INTT0 WATCH TIMER PROGRAM COUNTER * ALU CY PORT 2 BANK PORT 3 4 4 P20-P23 SP(8) PORT 0 PORT 1 4 4 P00-P03 P10-P13 P30-P33 BUZ/P23 PORT 4 4 4 P40-P43 INTW f LCD SI/SB1/P03 SO/SB0/P02 SCK/P01 CLOCKED SERIAL INTERFACE INTCSI INT0/P10 INT1/P11 INT2/P12 INT4/P00 KR0/P60 -KR7/P73 8 CLOCK OUTPUT CONTROL CLOCK DIVIDER INTERRUPT CONTROL fX / 2 BIT SEQ. BUFFER (16)
N
2. BLOCK DIAGRAM
PROGRAM MEMORY (ROM) 8064x8BITS : PD75308B 6016x8BITS : PD75306B 4096x8BITS : PD75304B
GENERAL REG.
PORT 5 PORT 6
P50-P53 P60-P63
DECODE AND CONTROL
4 4
DATA MEMORY (RAM) 512 x 4 BITS
PORT 7
P70-P73
24
S0-S23 S24/BP0 -S31/BP7
8 LCD CONTROLLER /DRIVER STAND BY CONTROL CPU CLOCK fLCD
PD75304B,75306B,75308B
4
COM0-COM3
SYSTEM CLOCK GENERATOR SUB MAIN
3
VLC0-VLC2 BIAS LCDCL/P30 SYNC/P31
PCL/P22
XT1 XT2 X1 X2
VDD
VSS RESET
*
13bits : PD75306B, 75308B 12bits : PD75304B
PD75304B,75306B,75308B
3. PIN FUNCTIONS
3.1 PORT PINS (1/2)
Pin Name P00 P01 P02 P03 P10 P11
Input/Output Input Input/output Input/output Input/output
DualFunction Pin INT4 SCK SO/SB0 SI/SB1 INT0 INT1
Function
8-bit I/O
After Reset
I/O Circuit Type *1 B
4-bit input port (PORT 0) On-chip pull-up resistor can be specified for P01 to P03 as a 3-bit unit by software.
F -A x Input F -B M-C
With noise elimination function
Input P12 P13 P20 P21 Input/output P22 P23 P30 *2 P31 *2 Input/output P32 *2 P33 *2 -- -- PCL BUZ LCDCL SYNC INT2 TI0 PTO0 --
4-bit input port (PORT 1) On-chip pull-up resistor can be specified as a 4-bit unit by software.
x
Input
B -C
4-bit input/output port (PORT 2) On-chip pull-up resistor can be specified as a 4-bit unit by software.
x
Input
E-B
Programmable 4-bit input/output port (PORT 3) Input/output can be specified bit-wise. On-chip pull-up resistor can be specified as a 4-bit unit by software.
x
Input
E-B
P40 to P43 *2
Input/output
--
N-ch open-drain 4-bit input/output port (PORT 4) On-chip pull-up resistor can be specified bitwise (mask option). Open-drain: 10 V withstand voltage N-ch open-drain 4-bit input/output port (PORT 5) On-chip pull-up resistor can be specified bitwise (mask option). Open-drain: 10 V withstand voltage
High level (onchip pull-up resistor) or highimpedance
M
P50 to P53 *2
Input/output
--
High level (onchip pull-up resistor) or highimpedance
M
*
1.
: Schmitt trigger input
2. LED direct drive possible
9
PD75304B,75306B,75308B
3.1 PORT PINS (2/2)
Pin Name P60 P61
Input/Output
DualFunction Pin KR0 KR1
Function
8-bit I/O
After Reset
I/O Circuit Type *1
Input/output P62 P63 P70 P71 Input/output P72 P73 BP0 BP1 Output BP2 BP3 BP4 BP5 Output BP6 BP7 S30 S31 S26 S27 S28 S29 KR6 KR7 S24 S25 KR2 KR3 KR4 KR5
Programmable 4-bit input/output port (PORT 6) Input/output can be specified bit-wise. On-chip pull-up resistor can be specified as a 4-bit unit by software.
Input
F -A
4-bit input/output port (PORT 7) On-chip pull-up resistor can be specified as a 4-bit unit by software.
Input
F -A
1-bit output port (BIT PORT) Also used as segment output pin.
x
*2
G-C
*
1.
: Schmitt trigger input However, the output level depends on BP0 to BP7 and VLC1 external circuit.
2. BP0 to BP7 select VLC1 as the input source.
Example
BP0 to BP7 are connected mutually within the PD75308B. Therefore, the output level of BP0 to BP7 is determined by the value of R1, R2 and R3.
PD75308B
VDD
R2 BP0 ON VLC1 R1 ON BP1 R3
10
PD75304B,75306B,75308B
3.2 NON-PORT PINS
Pin Name TI0 PTO0 PCL BUZ SCK SO/SB0 SI/SB1
Input/Output Input Input/output Input/output Input/output Input/output Input/output Input/output
DualFunction Pin P13 P20 P22 P23 P01 P02 P03
Function External event pulse input pin to timer/event counter Timer/event counter output pin Clock output pin Fixed frequency output pin (for buzzer or system clock trimming) Serial clock input/output pin Serial data output pin Serial bus input/output pin Serial data input pin Serial bus input/output pin Edge detection vectored interrupt input pin (both rising edge and falling edge detection effective) Edge detection vectored interrupt input pin (detection edge selectable) Edge detection testable input pin (rising edge detection) Clock synchronous system Asynchronous Asynchronous
After Reset Input Input Input Input Input Input
I/O Circuit Type *1 B -C E-B E-B E-B F -A F -B
Input
M -C
INT4
Input
P00
Input
B
INT0 Input INT1 INT2 KR0 to KR3 KR4 to KR7 S0 to S23 S24 to S31 COM0 to COM3 VLC0 to VLC2 BIAS LCDCL *4 SYNC *4 Input Input/output Input/output Output Output Output -- Output Input/output Input/output
P10 P11 P12 P60 to P63 P70 to P73 -- BP0 to BP7 -- -- -- P30 P31
Input
B -C
Input Input Input *2 *2 *2 -- *3 Input Input
B -C F -A F -A G-A G-C G-B -- -- E-B E-B
Parallel falling edge detection testable input pin Parallel falling edge detection testable input pin Segment signal output pin Segment signal output pin Common signal output pin LCD drive power supply pin On-chip split resistor (mask option) External split resistor cut output pin External expansion driver drive clock output pin External expansion driver synchronization clock output pin Main system clock oscillation crystal/ceramic connection pin. For external clock, the external clock signal is input to X1 and its opposite phase is input to X2. Subsystem clock oscillation crystal connection pin. For external clock, the external clock signal is input to XT1 and XT2 is opened. XT1 can be used as a 1-bit input (test) pin. System reset input pin NO CONNECTION Positive power supply pin GND potential pin
X1, X2
Input
--
--
--
XT1 XT2 RESET NC *5 VDD VSS
Input -- Input -- -- --
-- -- -- -- -- --
--
--
-- -- -- --
B -- -- --
*
1.
: Schmitt trigger input S0 to S31: VLC1, COM0 to COM2: VLC2, COM3: VLC0 However, the level of each display output depends on the display output and VLCX external circuit.
2. Display outputs are selected with VLCX shown below as the input source.
11
PD75304B,75306B,75308B
* 3. On-chip split resistor ........ Low level No on-chip split resistor ... High-impedance 4. Pins provided for system expansion. Currently, only used as P30 and P31. 5. If a printed wiring board is shared with the PD75P316A/75P316B, the NC pin should be connected to VDD.
12
PD75304B,75306B,75308B
3.3 PIN INPUT/OUTPUT CIRCUITS The input/output circuits of each pin of the PD75308B are shown by in abbreviated form.
TYPE A (For TYPE E-B) TYPE D (For TYPE E-B, F-A) VDD VDD data P-ch IN N-ch output disable N-ch P-ch OUT
Push-pull output that can be made high-impedance output CMOS Standard Input Buffer TYPE B (P-ch and N-ch OFF) TYPE E-B
VDD P.U.R. P.U.R. enable data Type D output disable P-ch
IN
IN/OUT
Type A
P.U.R.:Pull-Up Resistor
Schmitt-Trigger Input with Hysteresis Characteristic
TYPE B-C
TYPE F-A
VDD
VDD P.U.R. P.U.R. enable
P.U.R. enable data Type D output disable
P.U.R. P-ch
P-ch
IN/OUT
IN
Type B
P.U.R. : Pull-Up Resistor
P.U.R.:Pull-Up Resistor
13
PD75304B,75306B,75308B
TYPE F-B
VDD P.U.R. P.U.R. enable P-ch VDD P-ch
TYPE G-C VDD P-ch VLC0 VLC1 P-ch SEG data/Bit Port data VLC2 N-ch OUT N-ch
output disable (P) data output disable output disable (N)
IN/OUT
N-ch
P.U.R.:Pull-Up Resistor
TYPE G-A
TYPE M
VDD P.U.R. enable (Mask Option)
IN/OUT
VLC0 P-ch VLC1 P-ch SEG data N-ch VLC2 N-ch
Middle-High Voltage Input Buffer (+10 V Withstand Voltage) P.U.R.:Pull-Up Resistor
TYPE G-B TYPE M-C
data output disable
N-ch
OUT
VDD
VLC0 VLC1 P-ch N-ch P-ch
P.U.R. P.U.R. enable P-ch IN/OUT
OUT
data output disable
COM data N-ch VLC2 N-ch P-ch
N-ch
P.U.R.:Pull-Up Resistor
14
PD75304B,75306B,75308B
3.4 RECPMMENDED CONNECTION OF UNUSED PINS
5
Table 3-1 Connection of Unused Pins
Pin P00/INT4 P01/SCK P02/SO/SB0 P03/SI/SB1 P10/INT0-P12/INT2 Connect to VSS P13/TI0 P20/PTO0 P21 P22/PCL P23/BUZ P30/LCDCL P31/SYNC P32 P33 P40 to P43 P50 to P53 P60/KR0 to P63/KR3 P70/KR4 to P73/KR7 S0 to S23 S24/BP0 to S31/BP7 COM0 to COM3 VLC0 to VLC2 BIAS XT1 XT2 Connect to VSS Connect to VSS only when VLC0 to VLC2 are all unused; otherwise leave open Connect to VSS or VDD Leave open Leave open Input state : Connect to VSS or VDD Leave open Connect to VSS or VDD Recommended Connection Connect to VSS
Outputstate :
15
PD75304B,75306B,75308B
5
3.5 PRECAUTIONS CONCERNING P00/INT4 PIN AND RESET PIN In addition to the functions shown in 3.1 and 3.2, the P00/INT4 pin and RESET pin are also used to set the test mode for testing internal PD75308B operation (for IC testing). The test mode is set when a voltage greater than VDD is applied to either of these pins. Consequently, if noise exceeding VDD is applied during normal operation, the test mode may be entered, making it impossible for normal operation to continue. For example, misoperation may result if inter-wiring noise is applied to the P00/INT4 or RESET pin due to the length of the wiring from these pins, and the pin voltage exceeds VDD. Wiring should therefore be carried out so that inter-wiring noise is suppressed as far as possible. If it is completely impossible to suppress noise, noise prevention measures should be taken using an external component as shown below.
o Diode connected between P00/INT4 or RESET and VDD
o Capacitor connected between P00/INT4 or RESET and VDD
VDD Diode with Small VF P00/INT4, RESET
VDD
VDD
VDD P00/INT4, RESET
4. MEMORY CONFIGURATION * Program memory (ROM) ... 8064 x 8 bits (0000H to 1F7FH): PD75308B
6016 x 8 bits (0000H to 177FH): PD75306B 4096 x 8 bits (0000H to 0FFFH): PD75304B * 0000H to 0001H: Vector table in which the program start address after a reset is written. * 0002H to 000BH: Vector table in which program start addresses in case of interrupts are written. * 0020H to 007FH: Table area referenced by the GETI instruction.
* Data memory
* Data area ... 512 x 4 bits (000H to 1FFH) * Peripheral hardware area ... 128 x 4 bits (F80H to FFFH)
16
PD75304B,75306B,75308B
Fig. 4-1 Program Memory Map (a) PD75308B
Address 7 0000H 6 5 0 0 Internal Reset Start Address (High-Order 5 Bits) Internal Reset Start Address (Low-Order 8 Bits) 0002H MBE 0 0 INTBT/INT4 Start Address (High-Order 5 Bits) INTBT/INT4 Start Address (Low-Order 8 Bits) 0004H MBE 0 0 INT0 Start Address (High-Order 5 Bits) INT0 Start Address (Low-Order 8 Bits) 0006H MBE 0 0 INT1 Start Address (High-Order 5 Bits) INT1 Start Address (Low-Order 8 Bits) 0008H MBE 0 0 INTCSI Start Address (High-Order 5 Bits) INTCSI Start Address (Low-Order 8 Bits) 000AH MBE 0 0 INTT0 Start Address (High-Order 5 Bits) INTT0 Start Address (Low-Order 8 Bits) BRCB ! caddr Instruction Branch Address CALLF ! faddr Instruction Entry Address CALL !addr Instruction Subroutine Entry Address MBE 0
BR !addr Instruction Branch Address
0020H GETI Instruction Reference Table 007FH 0080H
BR $addr Instruction Relative Branch Address (-15 to -1, +2 to +16)
07FFH 0800H
Branch Destination Address and Subroutine Entry Address by GETI Instruction
0FFFH 1000H
1F7FH
BRCB ! caddr Instruction Branch Address
17
PD75304B,75306B,75308B
(b) PD75306B
Address 7 0000H 6 5 0 0 Internal Reset Start Address (High-Order 5 Bits) Internal Reset Start Address (Low-Order 8 Bits) 0002H MBE 0 0 INTBT/INT4 Start Address (High-Order 5 Bits) INTBT/INT4 Start Address (Low-Order 8 Bits) 0004H MBE 0 0 INT0 Start Address (High-Order 5 Bits) INT0 Start Address (Low-Order 8 Bits) 0006H MBE 0 0 INT1 Start Address (High-Order 5 Bits) INT1 Start Address (Low-Order 8 Bits) 0008H MBE 0 0 INTCSI Start Address (High-Order 5 Bits) INTCSI Start Address (Low-Order 8 Bits) 000AH MBE 0 0 INTT0 Start Address (High-Order 5 Bits) INTT0 Start Address (Low-Order 8 Bits) BRCB ! caddr Instruction Branch Address CALLF ! faddr Instruction Entry Address CALL !addr Instruction Subroutine Entry Address MBE 0
BR !addr Instruction Branch Address
0020H GETI Instruction Reference Table 007FH 0080H
BR $addr Instruction Relative Branch Address (-15 to -1, +2 to +16)
07FFH 0800H
Branch Destination Address and Subroutine Entry Address by GETI Instruction
0FFFH 1000H
177FH
BRCB ! caddr Instruction Branch Address
18
PD75304B,75306B,75308B
(c) PD75304B
Address 7 0000H 6 5 0 0 Internal Reset Start Address (High-Order 4 Bits) Internal Reset Start Address (Low-Order 8 Bits) 0002H MBE 0 0 INTBT/INT4 Start Address (High-Order 4 Bits) INTBT/INT4 Start Address (Low-Order 8 Bits) 0004H MBE 0 0 INT0 Start Address (High-Order 4 Bits) INT0 Start Address (Low-Order 8 Bits) 0006H MBE 0 0 INT1 Start Address (High-Order 4 Bits) INT1 Start Address (Low-Order 8 Bits) 0008H MBE 0 0 INTCSI Start Address (High-Order 4 Bits) INTCSI Start Address (Low-Order 8 Bits) 000AH MBE 0 0 INTT0 Start Address (High-Order 4 Bits) INTT0 Start Address (Low-Order 8 Bits) BR $addr Instruction Relative Branch Address (-15 to -1, +2 to +16) CALLF ! faddr Instruction Entry Address CALL !addr Instruction Subroutine Entry Address MBE 0
BR !caddr Instruction Branch Address
0020H GETI Instruction Reference Table 007FH 0080H
07FFH 0800H
Branch Destination Address and Subroutine Entry Address by GETI Instruction
0FFFH
19
PD75304B,75306B,75308B
Fig. 4-2 Data Memory Map
Data Memory General Register Area 000H (8 x 4) 007H 008H Stack Area
Memory Bank
0 256 x 4 (248 x 4) 0FFH
Data Area Static RAM (512 x 4)
100H 256 x 4 (224 x 4) 1DFH 1E0H 1
Display Data Memory Area 1FFH
(32 x 4)
Not On-Chip F80H 128 x 4
Peripheral Hardware Area
15
FFFH
20
PD75304B,75306B,75308B
5. PERIPHERAL HARDWARE FUNCTIONS
5.1 PORTS
There are four kinds of I/O ports, as follows.
* * * *
CMOS input (PORT0, 1) CMOS input/output (PORT2, 3, 6, 7) N-ch open drain (PORT4, 5) CMOS output (BP0 to BP7) Total
:8 : 16 :8 :8 40
Fig. 5-1 Port Functions
Port (Symbol) Function Operation/Features Remarks Dual function as INT4, SCK, SO/ SB0 & SI/SB1 pins Dual function as pins INT0 to INT2 & TI0 Dual function as PTO0, PCL & BUZ pins Dual function as pins KR4 to KR7 Dual function as LCDCL & SYNC pins Can be set to input or output mode bit-wise. PORT 6 Dual function as pins KR0 to KR3 4-bit input/output (N-ch open-drain 10 V withstand voltage)
PORT 0 4-bit input PORT 1
Always readable or testable irrespective of dual-function pin operating mode.
PORT 2
PORT 7 4-bit input/output PORT 3 *
Can be set to input or output mode as 4-bit unit. Ports 6 & 7 can be paired for 8-bit data input/output.
PORT 4 * PORT 5 *
Can be set to input or output mode as 4-bit unit. Ports 4 & 5 can be paired for 8-bit data input/output.
Incorporation of pull-up resistor can be specified bit-wise by mask option.
BP0 to BP7
1-bit output
Outputs data bit-wise. Switchable by software with LCD drive segment outputs S24 to S31.
Small drive capability. For CMOS load drive.
*
Direct LED drive capability
21
PD75304B,75306B,75308B
5.2 CLOCK GENERATOR The operation of the clock generator is determined by the processor clock control register (PCC) and system clock control register (SCC). There are two kinds of clock, the main system clock and subsystem clock, and the instruction execution time can be changed. * 0.95 s/1.91 s/15.3 s (4.19 MHz main system clock operation) * 122 s (32.768 kHz subsystem clock operation) Fig. 5-1 Clock Generator Block Diagram
XT1 VDD XT2 X1 VDD X2 Main System Clock Oscillation Circuit fX 1/2 1/16 1/8 to 1/4096 Frequency Divider Subsystem Clock Oscillation Circuit fXT LCD Controller/ Driver Watch Timer * Basic Interval Timer (BT) * Timer/Event Counter * Serial Interface * Watch Timer * LCD Controller/Driver * INT0 Noise Elimination Circuit * Clock Output Circuit
WM. 3 SCC SCC3
Oscillation Stop
Selector
Selector
Frequency Divider 1/4
* CPU * INT0 Noise Elimination Circuit * Clock Output Circuit
Internal Bus
SCC0 PCC PCC0 PCC1 4 HALT * STOP * PCC2, PCC3 Clear PCC2 PCC3 R
HALT F/F S
Q
STOP F/F Q S
Wait Release Signal from BT
RESET Signal R Standby Release Signal from Interrupt Control Circuit
Remarks
1. 2. 3. 4. 5. 6.
fX = Main system clock frequency fXT = Subsystem clock frequency PCC: Processor clock control register SCC: System clock control register * indicates instruction execution. One clock cycle (tCY) is one machine cycle. See "AC CHARACTERISTICS" in 11. "ELECTRICAL SPECIFICATIONS" for details of tCY.
5
22
PD75304B,75306B,75308B
5.3 CLOCK OUTPUT CIRCUIT The clock output circuit is a circuit which outputs a clock pulse from P22/PCL pin and is used to supply clock pulses to remote control outputs or peripheral LSI's.
* Clock output (PCL) : 524, 262, 65.5 kHz (at 4.19 MHz operation) * Buzzer output (BUZ): 2 kHz (at 4.19 MHz or 32.768 kHz operation)
The configuration of the clock output circuit is shown below.
Fig. 5-2 Clock Output Circuit Configuration
From Clock Generator
fX/2 fX/2 fX/2
3
Output Buffer Selector PCL/P22
4
6
PORT2.2 CLOM3 0 CLOM1CLOM0 CLOM P22 Output Latch
Bit 2 of PMGB Bit Specified In Port 2 Input/Output Mode
4 Internal Bus
Remarks
Consideration is given so that a low amplitude pulse is not output when switching between clock output enable and disable.
23
PD75304B,75306B,75308B
5.4 BASIC INTERVAL TIMER The basic interval timer includes the following functions.
* * * *
It operates as an interval timer which generates reference time interrupts. It can be applied as a watchdog timer which detects when a program is out of control. Selects and counts wait times when the standby mode is released. It reads count contents. Fig. 5-3 Basic Interval Timer Configuration
From Clock Generator fX/2
5
Clear
Clear
fX/2
7
MPX fX/2 fX/2
9
Basic Interval Timer (8-Bit Frequency Divider)
Set
BT Interrupt Request Flag
12
BT
IRQBT
Vectored Interrupt Request Signal
3 Wait Release Signal During Standby Release
BTM3
BTM2
BTM1
BTM0 BTM
*SET1
4 Internal Bus
8
Remarks
* indicates instruction execution.
24
PD75304B,75306B,75308B
5.5 WATCH TIMER The PD75308B incorporates a single watch timer channel. The watch timer has the following functions.
* Sets test flags (IRQW) at 0.5 second intervals. The standby mode can be released with IRQW. * 0.5 sec. time intervals can be created in either the main system clock or the subsystem clock. * In the fast watch mode, time intervals which are 128 times normal (3.91 ms) can be set, making this
function convenient for program debugging and testing.
* A fixed frequency (2.048 kHz) can be output to the P23/BUZ pin for use in generating buzzer sounds and
trimming system clock oscillation frequencies.
* The frequency divider can be cleared, so this clock can be started at 0 second.
Fig. 5-4 Watch Timer Block Diagram
fW 6 2
(512 Hz : 1.95 ms) fLCD
fW (256 Hz : 3.91 ms) 7 2 fW 128 (32.768 kHz) fXT (32.768 kHz) Selector INTW IRQW Set Signal
From Clock Generator
Selector
fW
(32.768 kHz)
fW 14 2 Frequency Divider 2Hz 0.5 sec fW 16 (2.048 kHz) Clear
Output Buffer P23/BUZ
WM WM7 0 0 0 WM3 WM2 WM1 WM0
PORT2.3 P23 Output Latch
Bit 2 of PMGB Port 2 Input/Output Mode
8
Bit Test Instruction
Internal Bus
Remarks
Values in parentheses are when fX = 4.194304 MHz and fXT = 32.768 kHz.
25
PD75304B,75306B,75308B
5.6 TIMER/EVENT COUNTER The PD75308B incorporates a single timer/event counter channel. The timer/event counter has the following functions.
* * * * * *
Operates as a programmable interval timer. Outputs square waves in the desired frequency to the PTO0 pin. Operates as an event counter. Divides the TI0 pin input into N divisions and outputs it to the PTO0 pin (frequency divider operation). Supplies a serial shift clock to the serial interface circuit. Count status read function.
26
Fig. 5-5 Timer/Event Counter Block Diagram
Internal Bus SET1 8
TM06 TM05 TM04 TM03 TM02
*1
TM0
8 8 Modulo Register (8) TMOD0 TOE0 TO Enable Flag PORT2.0 Bit 2 of PGMB Port 2 P20 Input/ Output Output Latch Mode To Serial Interface TOUT F/F Reset T0 Output Buffer INTT0 IRQT0 Set Signal P20/PTO0
PORT1.3
8 Comparator (8)
Match
Input Buffer P13/TI0 *2 From Clock Generator MPX
8
Count Register (8) CP Clear
PD75304B,75306B,75308B
Timer Operation Start RESET IRQT0 Clear Signal
*
1 SET1: Instruction execution 2 For detail, see Fig. 5-1.
27
PD75304B,75306B,75308B
5.7 SERIAL INTERFACE The PD75308B incorporates a clocked 8-bit serial interface. The serial interface has the following three modes.
* 3-wire serial I/O mode * 2-wire serial I/O mode * SBI mode (serial bus interface mode)
28
Fig. 5-6 Serial Interface Block Diagram
Internal Bus 8/4 Bit Test CSIM 8 8 8
Slave Address Register (SVA)
Bit Manipulation (8) Match Signal (8) RELT CMDT SBIC
Bit Test
Addres Comparator P03/SI/SB1
Selector
Shift Register (SIO)
(8)
SO SET CLR Latch D Q
ACKT ACKE BSYE
P02/SO/SB0
Selector
Busy/ Acknowledge Output Circuit Bus Release/ Command/ Acknowledge Detection Circuit RELD CMDD ACKD
P01/SCK
Serial Clock Counter P01 Output Latch
INTCSI Control Circuit
IRQCSI Set Signal
INTCSI
PD75304B,75306B,75308B
Serial Clock Control Circuit
Serial Clock Slector
fX/24 fX/2 6 fX/2 TOUT F/F (From Timer/ Event Counter) External SCK
3
29
PD75304B,75306B,75308B
5.8 LCD CONTROLLER/DRIVER The PD75308B has an on-chip display controller which generates segment signals and common signals in accordance with data in display data memory as well as a segment driver and common driver capable of directly driving the LCD panel. The configuration of the LCD controller/driver is shown in Fig. 5-7 The functions of the on-chip LCD controller/driver of the PD75308B are as follows.
* Display data memory are read automatically through DMA operations and segment signals and common
signals are generated.
* 5 different display modes can be selected. Static 1/2 duty (1/2 bias) 1/3 duty (1/2 bias)
4
1/3 duty (1/3 bias)
1/4 duty (1/3 bias) * In each of the display modes, 4 types of frame frequency can be selected. * The segment signal output is a maximum of 32 segments (S0 to S31) and 4 common outputs (COM0 to
COM3). * Segment signal outputs (S24 to S27, S28 to S31) are in 4-segment units and they can be switched for use as output ports (BP0 to BP3, BP4 to BP7).
* Split resistors can be built-in for the LCD driver power supply (mask option).
* Conformity to various bias methods and LCD driver voltages is possible. * When the display is OFF, the current flowing to the split resistors is cut.
* Display data memory not used for the display can be used as ordinary data memory. * Operation by the subsystem clock is also possible.
.
30
Fig. 5-7 LCD Controller/Driver Block Diagram
4 Display Data Memory
1FFH 3 2 1 0 3 1FEH 2 1 0 3 1E9H 2 1 0 3 1E8H 2 1 0 1E0H 32 10
8 Display Mode Register
4
Display Control Register
4
Port 3 Output Latch 10
8
Port Mode Register Group A
1
0
3
2
1
0
3
2
1
0
3
2
1
0
3
2
1
0
32
10
Timing Controller
fLCD Multiplexer
PD75304B,75306B,75308B
Selector
Segment Driver
Common Driver
LCD Driver Voltage Control
S31/PB7
S30/PB6
S24/PB0
S23
S0
COM3 COM2COM1COM0 V
LC2
VLC1
VLC0 P31/ P30/ SYNC LCDCL
31
PD75304B,75306B,75308B
5.9 BIT SEQUENTIAL BUFFER ..... 16 BITS The bit sequential buffer is special data memory for bit manipulations and can be used easily particularly for bit manipulations where addresses and bit specifications are changed sequentially, so it is convenient for processing data with long bit lengths bit-wise. Fig. 5-8 Bit Sequential Buffer Format
FC3H 3 2 1 BSB3 0 3 2 FC2H 1 BSB2 0 3 2 FC1H 1 0 3 2 FC0H 1 0 BSB0
Address Bit Symbol
BSB1
L Register L = F
L=CL=B INCS L
L=8L=7 DECS L
L=4 L=3
L=0
Remarks
In pmem.@L addressing, the specified bit corresponding to the L register is moved.
6. INTERRUPT FUNCTION
The PD75218has 8 interrupt sources, and prioritized multiple interrupts are possible. There are also two test sources, of which INT2 is an edge-detected testable input. The PD75218 interrupt control circuit has the following functions
* Hardware control vectored interrupt function that can control interrupt acceptance by interrupt flag * * * *
(IExxx) and interrupt master enable flag (IME). Arbitrary setting of interrupt start address. Multiple interrupt function with priority specifiable by the interrupt priority selection register (IPS). Interrupt request flag (IRQxxx) test function (interrupt generation confirmation by software possible). Standby mode release (selection of interrupt that releases the standby mode by interrupt enable flag possible).
32
Fig. 6-1 Interrupt Control Circuit Block Diagram
Internal Bus 2 IM2 1 IM1 3 IM0 Interrupt Enable Flag (IEXXX) IME IST0
INT BT INT4 /P00 INT0 /P10 INT1 /P11 *
Both Edges Detection Circuit Edge Detection Circuit Edge Detection Circuit
Decoder IRQBT IRQ4 IRQ0 IRQ1 IRQCSI IRQT0 Priority Control Circuit Vector Table Address Generator VRQn
INTCSI INTT0 INTW INT2 /P12 KR0/P60 KR7/P73
Rising Edge Detection Circuit Falling Edge Detection Circuit
PD75304B,75306B,75308B
IRQW
Selector
IRQ2 Standby Release Signal
IM2
*
Noise elimination circuit
33
PD75304B,75306B,75308B
7. STANDBY FUNCTION
To reduce the power consumption during program wait, the PD75308B has two standby modes: STOP mode and HALT mode.
Table 7-1 Operation Status at Standby Mode
STOP Mode Setting instruction STOP instruction HALT Mode HALT instruction Main system clock or subsystem clock settable Only CPU clock stopped (oscillation continued)
System clock at setting
Only main system clock settable
Clock oscillator
Only main system clock oscillation stopped
Basic interval timer
Stopped
Operating (IRQBT set at reference time intervals)*
Serial interface Operation Status
Operable only when external SCK input selected as serial clock
Operable*
Timer/event counter
Operable only when TI0 pin input specified as count clock
Operable*
Operable only when fXT selected as Watch timer count clock Operable only when fXT selected as LCDCL INT1, 2, 4: Operable Only INT0 inoperable Stopped Interrupt request signal from operable hardware enabled by interrupt enable flag, or RESET input
Operable
LCD controller
Operable
External interrupt
CPU
Release signal
Interrupt request signal from operable hardware enabled by interrupt enable flag, or RESET input
*
In-operable only with main system clock oscillation stopped.
34
PD75304B,75306B,75308B
8. RESET FUNCTION
The PD75308B is reset and the hardware is initialized as shown in Table 8-1 by RESET input. The reset operation timing is shown in Fig. 8-1. Fig. 8-1 Reset Operation by RESET Input
Wait (31.3 ms/4.19 MHz) RESET Input
Operating Mode or Standby Mode
HALT Mode
Operating Mode
Internal Reset Operation
Table 8-1 Status of Each Hardware after Resetting (1/2)
Hardware
RESET Input in Standby Mode Low-order 5(4)*1 bits of program memory address 0000H are set in PC12(11)*1 to 8 and the contents of address 0001H are set in PC7 to 0. Held 0 0 Bit 7 of program memory address 0000H is set in MBE. Undefined Held*2
RESET Input during Operation Low-order 5(4)*1 bits of program memory address 0000H are set in PC12(11)*1 to 8 and the contents of address 0001H are set in PC7 to 0. Undefined 0 0 Bit 7 of program memory address 0000H is set in MBE. Undefined Undefined
Program counter (PC)
Carry flag (CY) Skip flag (SK0 to 2) PSW Interrupt status flag (IST0)
Bank enable flag (MBE)
Stack pointer (SP) Data memory (RAM) General register (X, A, H, L, D, E, B, C) Bank selection register (MBS)
Held
Undefined
0
0
*
1. Figures in parentheses apply to the PD75304B. 2. Data of data memory addresses 0F8H to 0FDH becomes undefined by RESET input.
35
PD75304B,75306B,75308B
Table 8-1 Status of Each Hardware after Resetting (2/2)
Hardware
RESET Input in Standby Mode Undefined 0 0 FFH 0 0,0 0 Held 0 0 Held 0 0 0 0 0 Reset (0) 0 0 0, 0, 0 OFF Clear (0) 0
RESET Input during Operation Undefined 0 0 FFH 0 0,0 0 Undefined 0 0 Undefined 0 0 0 0 0 Reset (0) 0 0 0, 0, 0 OFF Clear (0) 0
Counter (BT) Basic interval timer Mode register (BTM) Counter (To) Timer/event counter Modulo register (TMOD0) Mode Register (TM0) TOE0, TOUT F/F Watch timer Mode register (WM) Shift register (SIO) Serial interface Operating mode register (CSIM) SBI control register (SBIC) Slave address register (SVA) Processor clock control register (PCC) Clock generator, clock output circuit System clock control register (SCC) Clock output mode register (CLOM) Display mode register (LCDM) LCD controller Display control register (LCDC) Interrupt request flag (IRQxxx) Interrupt enable flag (IExxx) Interrupt function Interrupt master enable flag (IME) INT0, 1, 2 mode registers (IM0, 1, 2) Output buffer Output latch Digital port I/O mode register (PMGA, B) Pull-up resistor specification register (POGA) Bit sequential buffer (BSB0 to 3)
0
0
Held
Undefined
36
PD75304B,75306B,75308B
9. INSTRUCTION SET
(1) Operand identifier and description The operand is described in the operand field of each instruction in accordance with the description for the operand identifier of the instruction. (See the RA75X Assembler Package User's Manual Language Volume (EEU-730) for details.) When there are multiple elements in the description, one of the elements is selected. Upper case letters and symbols (+,-) are keywords and are described unchanged. For immediate data, a suitable value or label is described. Various register or flag symbols can be used as a label instead of mem, fmem, pmem, bit, etc. (See the PD75308 User's Manual (IEM-5016) for details). However, there are restrictions on the labels for which fmem and pmem can be used (see the table on the previous page).
Identifier reg regl rp rpl rp2 rpa rpal n4 n8 mem* bit fmem pmem X, A, B, C, D, E, H, L X, B, C, D, E, H, L XA, BC, DE, HL BC, DE, HL BC, DE HL, DE, DL DE, DL 4-bit immediate data or label 8-bit immediate data or label 8-bit immediate data or label 2-bit immediate data or label FB0H to FBFH, FF0H to FFFH immediate data or label FC0H to FFFH immediate data or label Description
PD75304B
addr caddr faddr taddr PORTn IExxx MBn
0000H to 0FFFH immediate data or lebel 0000H to 177FH immediate data or lebel 0000H to 1F7FH immediate data or lebel
PD75306B PD75308B
12-bit immediate data or label 11-bit immediate data or label 20H to 7FH immediate data (however, bit0 = 0) or label PORT 0 to PORT 7 IEBT, IECSI, IET0, IE0, IE1, IE2, IE4, IEW MB0, MB1, MB15
*
Only an even address can be written for mem in the case of 8-bit data processing.
37
PD75304B,75306B,75308B
(2) Operation description legend A : A register; 4-bit accumulator B : B register; C D E H L X XA BC DE HL PC SP CY PSW MBE PORTn IME IExxx MBS PCC * (xx) xxH : : : : : : : : : : : : : : : : : : : : C register; D register; E register; H register; L register; X register; 4-bit accumulator Register pair (XA); 8-bit accumulator Register pair (BC) Register pair (DE) Register pair (HL) Program counter Stack pointer Carry flag; bit accumulator Program status word Memory bank enable flag Portn (n = 0 to 7) Interrupt master enable flag Interrupt enable flag Memory bank selection register Processor clock control register
: Address, bit delimiter : Contents addressed by xx : Hexadecimal data
38
PD75304B,75306B,75308B
(3) Description of addressing area field symbols
*1 *2
MB = MBE * MBS (MBS = 0, 1, 15) MB = 0 MBE = 0 : MB = 0 (00H to 7FH) MB = 15 (80H to FFH) MBE = 1 : MB = MBS (MBS = 0, 1, 15) MB = 15, fmem = FB0H to FBFH, FF0H to FFFH MB = 15, pmem = FC0H to FFFH Data memory addressing
*3
*4 *5
PD75304B
*6
addr=0000H to 0FFFH addr=0000H to 177FH addr=0000H to 1F7FH
PD75306B PD75308B
*7
addr = (Current PC) -15 to (Current PC) -1 (Current PC) + 2 to (Current PC) + 16
PD75304B
*8
caddr= 0000H to 0FFFH caddr= 0000H to 0FFFH (PC12=0) or 1000H to 177FH (PC12=1) caddr=0000H to 0FFFH (PC12=0) or 1000H to 1F7FH (PC12=1)
PD75306B PD75308B
Program memory addressing
*9 *10
faddr = 0000H to 07FFH taddr = 0020H to 007FH
Remarks
1. MB indicates the accessible memory bank. 2. For *2, MB = 0 without regard to MBE and MBS. 3. For *4 and *5, MB = 15 without regard to MBE and MBS. 4. *6 to *10 indicate the addressable area.
(4) Explanation of machine cycle field S shows the number of machine cycles required when skip is performed by an instruction with skip. The value of S changes as follows: * No skip ....................................................................................................................................................................... S = 0 * When instruction to be skipped is 1-byte or 2-byte instruction ......................................................................... S = 1 * When instruction to be skipped is 3-byte instruction (BR !addr, CALL !addr instruction) ............................. S = 2 Note One machine cycle is required to skip a GETI instruction.
One machine cycle is equivalent to one cycle (=tCY) of the CPU clock . Three times can be selected by PCC setting.
39
PD75304B,75306B,75308B
Note
Mnemonic
Operand
Bytes
Machine Cycles 1 2 2 2 2 1 1 2 1 2 2 2 2 2 2 2 2 2 1 1 2 2 2 1 2 A n4 regl n4 XA n8 HL n8 rp2 n8 A (HL) A (rpal) XA (HL) (HL) A (HL) XA A (mem) XA (mem) (mem) A (mem) XA A reg XA rp regl A rpl XA A (HL) A (rpal) XA (HL) A (mem) XA (mem) A regl XA rp
Operation
Addressing Area
Skip Condition Stack A
A, #n4 regl, #n4 XA, #n8 HL, #n8 rp2, #n8 A, @HL A, @rpal XA, @HL MOV @HL, A @HL, XA A, mem Transfer XA, mem mem, A mem, XA A, reg XA, rp regl, A rpl, XA A, @HL A, @rpal XA, @HL XCH A, mem XA, mem A,regl XA, rp
1 2 2 2 2 1 1 2 1 2 2 2 2 2 2 2 2 2 1 1 2 2 2 1 2
Stack A Stack B
*1 *2 *1 *1 *1 *3 *3 *3 *3
*1 *2 *1 *3 *3
q PD75304B XA (PC11-8 + DE)ROM Table reference XA, @PCDE 1 3 q PD75306B, 75308B XA (PC12-8 + DE)ROM q PD75304B XA (PC11-8 + XA)ROM XA, @PCXA 1 3 q PD75306B, 75308B XA (PC12-8 + XA)ROM A A + n4 A A + (HL) A, CY A + (HL) + CY A A - (HL) A, CY A - (HL) - CY *1 *1 *1 *1 borrow carry carry
MOVT
A, #n4 Operation ADDS ADDC SUBS SUBC A, @HL A, @HL A, @HL A, @HL
1 1 1 1 1
1+S 1+S 1 1+S 1
Note
Instruction Group
40
PD75304B,75306B,75308B
Note Mne1 monic
Operand
Bytes
Machine Cycles 2 1 2 1 2 1 1 2 1+S 2+S 2+S 1+S 2+S 2+S 1+S 2+S 1 1 1+S 1 2 2 2 2 2 2 2 2 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S A A n4 A A (HL) A A n4 A A (HL) A A n4 A A (HL)
Operation
Addressing Area
Skip Condition
A, #n4 AND Operation A, @HL A, #n4 OR A, @HL A, #n4 XOR A, @HL Note 2 RORC NOT A A reg Note 3 INCS @HL mem DECS Comparison reg reg, #n4 SKE @HL, #n4 A, @HL A, reg SET1 Note 4 CLR1 SKT NOT1 CY CY CY CY mem.bit SET1 fmem.bit pmem.@L @H + mem.bit mem.bit Memory bit manipulation CLR1 fmem.bit pmem.@L @H + mem.bit mem.bit SKT fmem.bit pmem.@L @H + mem.bit mem.bit SKF fmem.bit pmem.@L @H + mem.bit
2 1 2 1 2 1 1 2 1 2 2 1 2 2 1 2 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
*1
*1
*1
CY A0, A3 CY, An-1 An AA reg reg + 1 (HL) (HL) + 1 (mem) (mem) + 1 reg reg - 1 Skip if reg = n4 Skip if (HL) = n4 Skip if A = (HL) Skip if A = reg CY 1 CY 0 Skip if CY = 1 CY CY (mem.bit) 1 (fmem.bit) 1 (pmem7-2 + L3-2.bit (L1-0)) 1 (H + mem3-0.bit) 1 (mem.bit) 0 (fmem.bit) 0 (pmem7-2 + L3-2.bit (L1-0)) 0 (H + mem3-0.bit) 0 Skip if (mem.bit) = 1 Skip if (fmem.bit) = 1 Skip if (pmem7-2 + L3-2.bit (L1-0)) = 1 Skip if (H + mem3-0.bit) = 1 Skip if (mem.bit) = 0 Skip if (fmem.bit) = 0 Skip if (pmem7-2 + L3-2.bit (L1-0)) = 0 Skip if (H + mem3-0.bit) = 0 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 (mem.bit) = 1 (fmem.bit) = 1 (pmem.@L) = 1
(@H + mem.bit) = 1
reg = 0 *1 *3 (HL) = 0 (mem) = 0 reg = FH reg = n4 *1 *1 (HL) = n4 A = (HL) A = reg
CY = 1
(mem.bit) = 0 (fmem.bit) = 0 (pmem.@L) = 0
(@H + mem.bit) = 0
Note
1. Instruction Group 2. Accumulator operation 3. Increment and decrement 4. Carry flag operation 41
PD75304B,75306B,75308B
Note
Mnemonic
Operand
Bytes
Machine Cycles
Operation
Addressing Area *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1
Skip Condition
fmem.bit SKTCLR pmem.@L @H + mem.bit Memory bit manipulation CY, fmem.bit AND1 CY, pmem.@L
CY, @H + mem.bit
2 2 2 2 2 2 2 2 2 2 2 2
2+S 2+S 2+S 2 2 2 2 2 2 2 2 2
Skip if (fmem.bit) = 1 and clear Skip if (pmem7-2 + L3-2.bit (L1-0)) = 1 and clear Skip if (H + mem3-0.bit) = 1 and clear CY CY (fmem.bit) CY CY (pmem7-2 + L3-2.bit (L1-0)) CY CY (H + mem3-0.bit) CY CY (fmem.bit) CY CY (pmem7-2 + L3-2.bit (L1-0)) CY CY (H + mem3-0.bit) CY CY (fmem.bit) CY CY (pmem7-2 + L3-2.bit (L1-0)) CY CY (H + mem3-0.bit) q PD75304B PC11-0 addr (The assembler selects the optimum instruction from among the BRCB !caddr, and BR $addr instructions.)
(fmem.bit) = 1 (pmem.@L) = 1
(@H + mem.bit) = 1
CY, fmem.bit OR1 CY, pmem.@L
CY, @H + mem.bit
CY, fmem.bit XOR1 CY, pmem.@L
CY, @H + mem.bit
addr
--
--
BR Branch
q PD75306B, 75308B PC12-0 addr (The assembler selects the optimum instruction from among the BR !addr, BRCB !caddr, and BR $addr instructions.) q PD75306B, 75308B PC12-0 addr q PD75304B PC11-0 addr
*6
!addr
3
3
*6
$addr
1
2
q PD75306B, 75308B PC12-0 addr q PD75304B PC11-0 caddr11-0
*7
BRCB
!caddr
2
2
q PD75306B, 75308B PC12-0 PC12 + caddr11-0 q PD75304B (SP - 4) (SP - 1) (SP - 2) PC11-0 (SP - 3) MBE, 0, 0, 0 PC11-0 addr, SP SP - 4
*8
Subroutine stack control
CALL
!addr
3
3
q PD75306B, 75308B (SP - 4) (SP - 1) (SP - 2) PC11-0 (SP - 3) MBE, 0, 0, PC12 PC12-0 addr, SP SP - 4
*6
Note
Instruction Group
42
PD75304B,75306B,75308B
Note Mnemonic 1
Operand
Bytes Machine Cycles
Operation
Addressing Area
Skip Condition
q PD75304B (SP - 4) (SP - 1) (SP - 2) PC11-0 (SP - 3) MBE, 0, 0, 0 PC11-0 0, faddr, SP SP - 4 CALLF !faddr 2 2 q PD75306B, 75308B (SP - 4) (SP - 1) (SP - 2) PC11-0 (SP - 3) MBE, 0, 0, PC12 PC12-0 00, faddr, SP SP - 4 q PD75304B MBE, x, x, x (SP + 1) PC11-0 (SP) (SP + 3) (SP + 2) SP SP + 4 RET 1 3 q PD75306B, 75308B MBE, x, x, PC12 (SP + 1) PC11-0 (SP) (SP + 3) (SP + 2) SP SP + 4 q PD75304B MBE, x, x, x (SP + 1) PC11-0 (SP) (SP + 3) (SP + 2) SP SP + 4 the skip unconditionally RETS 1 3+S q PD75306B, 75308B MBE, x, x, PC12 (SP + 1) PC11-0 (SP) (SP + 3) (SP + 2) SP SP + 4 the skip unconditionally q PD75304B MBE, x, x, x (SP + 1) PC11-0 (SP) (SP + 3) (SP + 2) PSW (SP + 4) (SP + 5), SP SP + 6 1 3 q PD75306B, 75308B MBE, x, x, PC12 (SP + 1) PC11-0 (SP) (SP + 3) (SP + 2) PSW (SP + 4) (SP + 5), SP SP + 6 (SP - 1) (SP - 2) rp, SP SP - 2 (SP - 1) MBS, (SP - 2) 0, SP SP - 2 rp (SP + 1) (SP), SP SP + 2 MBS (SP + 1), SP SP + 2 IME 1 IE x x x 1 IME 0 IE x x x 0 Unconditional *9
Subroutine stack control
RETI
rp PUSH BS rp POP BS
1 2 1 2 2
1 2 1 2 2 2 2 2
Note 2
EI
IE x x x
2 2
DI
IE x x x
2
Note
1. Instruction Group 2. Interrupt control
43
PD75304B,75306B,75308B
Note Mne1 monic
Operand
Bytes
Machine Cycles
Operation
Addressing Area
Skip Condition
Input/output
A, PORTn IN* XA, PORTn PORTn, A OUT* PORTn, XA HALT STOP NOP SEL MBn
2 2 2 2 2 2 1 2
2 2 2 2 2 2 1 2
A PORTn XA PORTn+1, PORTn PORTn A PORTn+1, PORTn XA Set HALT Mode (PCC.2 1) Set STOP Mode (PCC.3 1) No Operation MBS n (n = 0, 1, 15)
(n = 0-7) (n = 4, 6) (n = 2-7) (n =4, 6)
Note 2
q PD75304B * TBR Instruction PC11-0 (taddr) 3-0 + (taddr + 1) ----------------------------------------------------------------* TCALL Instruction (SP - 4) (SP - 1) (SP - 2) PC11-0 (SP - 3) MBE, 0, 0, 0 PC11-0 (taddr) 3-0 (taddr + 1) SP SP - 4 ----------------------------------------------------------------* Other than TBR and TCALL Instruction Special Execution of an instruction addressed at (taddr) and (taddr + 1) GETI taddr 1 3 q PD75306, 75308BB * TBR Instruction PC12-0 (taddr) 4-0 + (taddr + 1) ----------------------------------------------------------------* TCALL Instruction (SP - 4) (SP - 1) (SP - 2) PC11-0 (SP - 3) MBE, 0, 0, PC12 PC12-0 (taddr) 4-0 (taddr + 1) SP SP - 4 ----------------------------------------------------------------* Other than TBR and TCALL Instruction Execution of an instruction addressed at (taddr) and (taddr + 1) *10
-----------------------------
----------------------------Conforms to referenced instruction.
-----------------------------
----------------------------Conforms to referenced instruction.
*
At IN/OUT instruction execution, MBE = 0 or MBE = 1, MBS = 15 must be set in advance. 1. Instruction Group 2. CPU control The TBR and TCALL instructions are assembler pseudo-instructions for GETI instruction table definition.
Note
Remarks
44
PD75304B,75306B,75308B
10. MASK OPTION SELECTION
The following pin mask options are available.
Pin Functions P40 to P43, P50 to P53 VLC0 to VLC2, BIAS Mask Options q Pull-up resistor incorporated (specifiable bit-wise) q No pull-up resistor (specifiable bit-wise) q LCD drive power supply split resistor incorporated (specifiable as 4-bit unit) q No LCD drive power supply split resistor (specifiable as 4-bit unit)
45
PD75304B,75306B,75308B
11. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (Ta = 25 C)
PARAMETER Power supply voltage SYMBOL VDD VI1 Input voltage V12 Ports 4 and 5 Open-drain Output voltage Output current high VO One pin IOH All pins Peak value One pin rms Peak value Output current low IOL* Total of ports 0, 2, 3 and 5 rms Peak value Total of ports 4, 6, and 7 rms Operating temperature Storage temperature Topt 60 -40 to +85 mA C C 60 100 mA mA 15 100 mA mA -30 30 mA mA -0.3 to +11 -0.3 to VDD +0.3 -15 V V mA Except ports 4 and 5 On-chip pull-up resistor TEST CONDITIONS RATING -0.3 to +7.0 -0.3 to VDD +0.3 -0.3 to VDD +0.3 UNIT V V V
Tstg
-65 to +150
*
Rms is calculated using the following expression: [rms] = [peak value] x duty
CAPACITANCE (Ta = 25 C, VDD = 0 V)
PARAMETER Input capacitance Output capacitance I/O capacitance SYMBOL CIN COUT CIO f = 1 MHz Unmeasured pins returned to 0 V. TEST CONDITIONS MIN. TYP. MAX. 15 15 15 UNIT pF pF pF
46
PD75304B,75306B,75308B
MAIN SYSTEM CLOCK OSCILLATOR CHARACTERISTICS (Ta = -40 to +85 C, VDD = 2.0 to 6.0 V)
RESONATOR
RECOMMENDED CONSTANT
PARAMETER Oscillator frequency (fx)*1
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
1.0 After VDD reached the MIN. of the oscillation voltage range 1.0 VDD = 4.5 to 6.0 V 4.19
5.0*3
MHz
X1
X2
Ceramic resonator*3
C1 C2
Oscillation stabilization time*2
4
ms
VDD
Oscillator frequency (fx)*1
X1 X2
5.0*3
MHz
Crystal resonator*3
C1 C2
10
ms
Oscillation stabilization time*2 30 ms
VDD
X1
X2
X1 input frequency (fx)*1
1.0
5.0*3
MHz
External clock
PD74HCU04
X1 input high-/low-level width (tXH, tXL) 100 500 ns
*
1. The oscillator frequency and X1 input frequency indicate only the oscillator characteristics. For the instruction execution time refer to the AC characteristics. 2. The oscillation stabilization time is necessary for oscillation to stabilize after applying VDD or releasing the STOP mode. 3. When the oscillation frequency is 4.19 MHz < fX 5.0 MHz, PCC = 0011 should not be selected as the instruction execution time. If PCC = 0011 is selected, one machine cycle is less than 0.95 s, and the specification MIN. value of 0.95 s will not be achieved.
5
47
PD75304B,75306B,75308B
SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS (Ta = -40 to +85 C, VDD = 2.0 to 6.0 V)
RESONATOR
RECOMMENDED CONSTANT
PARAMETER
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
XT1
XT2 R
Oscillator frequency (fXT) VDD = 4.5 to 6.0 V Oscillation stabilization time*
32
32.768
35
kHz
Crystal resonator
C3
1.0
2
s
C4
10
VDD
s
XT1 input frequency (fXT)
XT1 XT2 Leave Open
32
100
kHz
External clock
XT1 input high-/ low-level width (tXTH,tXTL) 5 15
s
*
This is the time required for oscillation to stabilize after VDD reaches the MIN. value of the oscillation voltage range. When the main system clock and subsystem clock oscillators are used, the following should be noted concerning wiring in the area in the figure enclosed by a dotted line to prevent the influence of wiring capacitance, etc. * The wiring should be kept as short as possible. * No other signal lines should be crossed. Keep away from lines carrying a high fluctuating current. * The oscillator capacitor grounding point should be at the same potential as VDD. Do not ground to a ground pattern carrying a high current. * A signal should not be taken from the oscillator. The subsystem clock oscillator is a low-amplitude circuit in order to achieve a low consumption current, and is more prone to misoperation due to noise than the main system clock oscillator. Particular care is therefore required with the wiring method when the subsystem clock is used.
5 Note
48
PD75304B,75306B,75308B
DC CHARACTERISTICS (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V) (1/2)
PARAMETER SYMBOL VIH1 VIH2 Input voltage high VIH3 Ports 4 and 5 Open-drain VIH4 VIL1 Input voltage low VIL2 VIL3 X1, X2, XT1 Ports 2, 3, 4 and 5 Ports 0, 1, 6, 7 RESET X1, X2, XT1 VDD = 4.5 to 6.0 V IOH = -1 mA IOH = -100 A VDD = 4.5 to 6.0 V IOH = -100 A IOH = -30 A Ports 3, 4 and 5 VDD = 4.5 to 6.0 V IOL = 15 mA Ports 0, 2, 3, 4, 5, 6 and 7 VOL1 Output voltage low SB0, 1 VDD = 4.5 to 6.0 V IOL = 1.6 mA IOL = 400 A Open-drain pull-up resistor 1 k VDD = 4.5 to 6.0 V IOL = 100 A IOL = 50 A Other than below VIN = VDD Input leakage current high ILIH2 ILIH3 ILIL1 VIN = 0 V ILIL2 ILOH1 ILOH2 Output leakage current low VOUT = VDD VOUT = 10 V X1, X2, XT1 Other than below Ports 4 and 5 (when open-drain) -20 3 20 VIN = 10 V X1, X2, XT1 Ports 4 and 5 (when open-drain) Other than below 20 20 -3 0.7 VDD VDD -0.5 0 0 0 VDD -1.0 VDD -0.5 VDD -2.0 VDD -1.0 10 VDD 0.3 VDD 0.2 VDD 0.4 V V V V V V V V V Ports 2 and 3 Ports 0,1,6,7, RESET On-chip pull-up resistor TEST CONDITIONS MIN. 0.7 VDD 0.8 VDD 0.7 VDD TYP. MAX. VDD VDD VDD UNIT V V V
VOH1 Output voltage high VOH2
Ports 0, 2,3, 6, 7, BIAS
BP0 to BP7 (with 2 IOH outputs)
0.5
2.0
V
0.4 0.5 0.2 VDD
V V V
VOL2
BP0 to BP7 (with 2 IOL outputs)
1.0 1.0 3
V V
IL1H1
A A A A A A A A
Input leakage current low
Output leakage current high
ILOL
VOUT = 0 V
-3
49
PD75304B,75306B,75308B
DC CHARACTERISTICS (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V) (2/2)
PARAMETER SYMBOL TEST CONDITIONS Ports 0, 1, 2, 3, 6 and 7 (Except P00) VIN = 0 V Ports 4 and 5 VOUT = VDD -2.0 V VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 5.0 V 10% VDD = 3.0 V 10% MIN. 15 30 15 10 2.0 60 IO = 5 A 100 40 TYP. 40 MAX. 80 300 70 60 VDD 150 UNIT k k k k V k
RL1 On-chip pull-up resistor RL2
LCD drive voltage LCD split resistor LCD output voltage deviation*1 (common) LCD output voltage deviation (segment)
VLCD RLCD
VODC
VODS
IO = 1 A
VLCD0 = VLCD VLCD1 = VLCD x 2/3 VLCD2 = VLCD x 1/3 2.7 V VLCD VDD
0
0.2
V
0
0.2 3.0 0.4 600 180 40 12 1 0.5 9 1.2 1800 540 120 36 25 15 5
V
VDD = 5 V 10%*4 IDDI 4.19 MHz*3 crystal oscillation C1 = C2 = 22 pF IDD2 VDD = 3 V 10%*5 HALT mode VDD = 5 V 10% VDD = 3 V 10%
mA mA
A A A A A A A
Supply current*2
IDD3 IDD4 32 kHz*6 crystal oscillation
VDD = 3 V 10% HALT mode VDD = 3 V 10%
VDD = 5 V 10% IDD5 XT1 = 0 V STOP mode VDD = 3 V 10%
Ta = 25 C
0.5
*
1. The voltage deviation is the difference between the output voltage and the segment or common output desired value (VLCDn ; n= 0, 1, 2). 2. Current which flows in the on-chip pull-up resistor or LCD split resistor is not included. 3. Including oscillation of the subsystem clock. 4. When the processor clock control register (PCC) is set to 0011 and the device is operated in the highspeed mode. 5. When PCC is set to 0000 and the device is operated in the low-speed mode. 6. When the system clock control register (SCC) is set to 1001 and the device is operated on the subsystem clock, with main system clock oscillation stopped.
50
PD75304B,75306B,75308B
AC CHARACTERISTICS (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V)
PARAMETER CPU clock cycle time (minimum instruction execution time)*1 SYMBOL TEST CONDITIONS Operating on main system clock Operating on subsystem clock VDD = 4.5 to 6.0 V fTI 0 tTIH, tTIL VDD = 4.5 to 6.0 V 0.48 1.8 INT0 Interrupt input width high/low tINTH, tINTL INT1, 2, 4 KR0 to KR7 RESET width low tRSL *2 10 10 10 275 kHz VDD = 4.5 to 6.0 V MIN. 0.95 3.8 114 0 122 TYP. MAX. 64 64 125 1 UNIT
s s s
MHz
tCY
TI0 input frequency
TI0 input width high/low
s s s s s s
*
1. The CPU clock ( ) cycle time (minimum instruction execution time) is determined by the oscillatior frequency of the connected resonator, the system clock control register (SCC) and the processor clock control register (PCC). The figure at the right indicates the cycle time tCY versus supply voltage VDD characteristic with the main system clock operating. 2. 2tCY or 128/fX is set by setting the interrupt mode register (IM0).
tCY vs VDD (Operating on Main System Clock)
70 64 30 6 5 4
Guaranteed Operation Range
Cycle Time tCY [s]
3
2
1
0.5 0 1 2 3 4 5 6
Supply Voltage VDD [V]
51
PD75304B,75306B,75308B
SERIAL TRANSFER OPERATION 2-Wired and 3-Wired Serial I/O Modes (SCK ... Internal clock output): (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V)
PARAMETER SYMBOL TEST CONDITIONS VDD = 4.5 to 6.0 V SCK cycle time tKCY1 3800 SCK width high/ low SI setup time (to SCK) SI hold time (from SCK) SO output delay time from SCK tKL1 tKH1 VDD = 4.5 to 6.0 V tKCY1/2-50 tKCY1/2-150 150 ns ns ns ns MIN. 1600 TYP. MAX. UNIT ns
tSIK1
tKSI1 VDD = 4.5 to 6.0 V
400 250 1000
ns ns ns
tKSO1
RL = 1 k, CL = 100 pF*
2-Wired and 3-Wired Serial I/O Modes (SCK ... External clock input): (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V)
PARAMETER SYMBOL TEST CONDITIONS VDD = 4.5 to 6.0 V SCK cycle time tKCY2 3200 SCK width high/ low SI setup time (to SCK) SI hold time (from SCK ) SO output delay time from SCK tKL2 tKH2 VDD = 4.5 to 6.0 V 400 1600 100 ns ns ns ns MIN. 800 TYP. MAX. UNIT ns
tSIK2
tKSI2 VDD = 4.5 to 6.0 V
400 300 1000
ns ns ns
tKSO2
RL = 1 k, CL = 100 pF*
*
RL and CL are load resistor and load capacitance of the SO output line.
52
PD75304B,75306B,75308B
SBI Mode (SCK ... Internal clock output (Master)): (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V)
PARAMETER SYMBOL TEST CONDITIONS VDD = 4.5 to 6.0 V SCK cycle time tKCY3 3800 SCK width high/ low SB0, 1 setup time (to SCK ) SB0, 1 hold time (from SCK ) SB0, 1 output delay time from SCK SB0, 1 from SCK SCK from SB0, 1 SB0, 1 width low SB0, 1 width high tKL3 tKH3 VDD = 4.5 to 6.0 V tKCY3/2-50 tKCY3/2-150 150 ns ns ns ns MIN. 1600 TYP. MAX. UNIT ns
tSIK3
tKSI3 VDD = 4.5 to 6.0 V
tKCY3/2 0 0 tKCY3 tKCY3 tKCY3 tKCY3 250 1000
ns ns ns ns ns ns ns
tKSO3
RL = 1 k, CL = 100 pF*
tKSB tSBK tSBL tSBH
SBI Mode (SCK ... External clock input (Slave)): (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V)
PARAMETER SYMBOL TEST CONDITIONS VDD = 4.5 to 6.0 V SCK cycle time tKCY4 3200 SCK width high/ low SB0, 1 setup time (to SCK ) SB0, 1 hold time (from SCK ) SB0, 1 output delay time from SCK SB0, 1 from SCK SCK from SB0, 1 SB0, 1 width low SB0, 1 width high tKL4 tKH4 VDD = 4.5 to 6.0 V 400 1600 100 ns ns ns ns MIN. 800 TYP. MAX. UNIT ns
tSIK4
tKSI4 VDD = 4.5 to 6.0 V
tKCY4/2 0 0 tKCY4 tKCY4 tKCY4 tKCY4 300 1000
ns ns ns ns ns ns ns
tKSO4
RL = 1 k, CL = 100 pF*
tKSB tSBK tSBL tSBH
*
RL and CL are load resistor and load capacitance of the SB0, 1 output lines.
53
PD75304B,75306B,75308B
DC CHARACTERISTICS (Ta = -40 to +85 C, VDD = 2.0 to 6.0 V) (1/2)
PARAMETER SYMBOL VIH1 VIH2 Input voltage high VIH3 Ports 4 and 5 Open-drain VIH4 VIL1 Input voltage low VIL2 VIL3 VOH1 Output voltage high VOH2 X1, X2, XT1 Ports 2, 3, 4 and 5 Ports 0, 1, 6, 7, RESET X1, X2, XT1 Ports 0, 2, 3, 6, 7, BIAS BP0 to BP7 (with 2 IOH outputs) Ports 0, 2, 3, 4, 5 6, and 7 VOL1 Output voltage low VOL2 ILIH1 VIN = VDD Input leakage current high ILIH2 ILIH3 ILIL1 VIN = 0 V ILIL2 ILOH1 Output leakage current high ILOH2 VOUT = VDD VOUT = 10 V X1, X2, XT1 Other than below Ports 4 and 5 (with open-drain) -20 3 20 VIN = 10 V X1, X2, XT1 Ports 4 and 5 (with open-drain) Other than below 20 20 -3 SB0, 1 BP0 to BP7 (with 2 IOL outputs) Open-drain, pull-up resistor 1 k IOL = 10 A Other than below 0.2 VDD V IOH = -100 A IOH = -10 A IOL = 400 A 0.8 VDD VDD -0.3 0 0 0 VDD -0.5 10 VDD 0.2 VDD 0.2 VDD 0.3 V V V V V V TEST CONDITIONS Ports 2 and 3 Ports 0, 1, 6, 7, RESET On-chip pull-up resistor MIN. 0.8 VDD 0.8 VDD 0.8 VDD TYP. MAX. VDD VDD VDD UNIT V V V
VDD -0.4
V
0.5
V
0.4 3
V
A A A A A A A A
Input leakage current low
Output leakage current low
ILOL
VOUT = 0 V
-3
54
PD75304B,75306B,75308B
DC CHARACTERISTICS (Ta = -40 to +85 C, VDD = 2.0 to 6.0 V) (2/2)
PARAMETER SYMBOL TEST CONDITIONS Ports 0, 1, 2, 3, 6 and 7 (Except P00) VIN = 0 V Ports 4 and 5 VOUT = VDD -1.0 V VDD = 2.5 V 10% MIN. TYP. MAX. UNIT
RL1 On-chip pull-up resistor RL2 LCD drive voltage LCD split resistor LCD output voltage deviation *1 (common) LCD output voltage deviation (segment) VLCD RLCD
50
600
k
VDD = 2.5 V 10%
10 2.0 60 100
60 VDD 150 0.2
k V k
VODC
IO = 5 A
VODS
IO = 1 A
VLCDO = VLCD VLCD1 = VLCD x 2/3 VLCD2 = VLCD x 1/3 2.0 V VLCD VDD
0
V
0
0.2
V
VDD = 3 V 10%*4 IDDI 4.19 MHz*3 crystal oscillation C1 = C2 = 22 pF low-speed mode VDD = 2.5 V 10%*4 HALT mode VDD = 3 V 10% VDD = 2.5 V 10%
0.4 0.3 180 120 40 25 12 9 0.5
1.2 0.9 540 360 120 75 36 27 15 5 15 5
mA mA
A A A A A A A A A A
IDD2
VDD = 3 V 10% IDD3 Supply current*2 32 kHz*5 crystal oscillation IDD4 mode VDD = 2.5 V 10% HALT VDD = 3 V 10% VDD = 2.5 V 10%
VDD = 3 V 10% IDD5 XT1 = 0 V STOP mode
Ta = 25 C
0.5 0.4
VDD = 2.5 V 10%
Ta = 25C
0.4
*
1. The voltage deviation is the difference between the output voltage and the segment or common output desired value (VLCDn; n = 0, 1, 2). 2. Current which flows in the on-chip pull-up resistor or LCD split resistor is not included. 3. Including oscillation of the subsystem clock. 4. When PCC is set to 0000 and the device is operated in the low-speed mode. 5. When the system clock control register (SCC) is set to 1001 and the device is operated on the subsystem clock, with main system clock oscillation stopped.
55
PD75304B,75306B,75308B
AC CHARACTERISTICS (Ta = -40 to +85 C, VDD = 2.0 to 6.0 V)
PARAMETER SYMBOL TEST CONDITIONS VDD = 2.7 to 6.0 V CPU clock cycle time (minimum instruction execution time)*1 Operation on main system clock tCY VDD = 2.0 to 6.0 V Ta = -40 to + 60 C VDD = 2.2 to 6.0 V MIN. 3.8 5 3.4 TYP. MAX. 64 64 64 UNIT
s s s s
Operation on subsystem clock TI0 input frequency TI0 input width high/low fTI tTIH, tTIL INT0 Interrupt input width high/low tINTH, tINTL INT1, 2, 4 KR0 to KR7 RESET width low tRSL
114
122
125
0
275
kHz
1.8 *2 10 10 10
s s s s s
*
1. The CPU clock ( ) cycle time (minimum instruction execution time) is determined by the oscillatior frequency of the connected resonator, the system clock control register (SCC) and the processor clock control register (PCC). The figure at the right indicates the cycle time tCY versus supply voltage VDD characteristic with the main system clock operating. 2. 2tCY or 128/fX is set by setting the interrupt mode register (IM0).
Cycle Time tCY [s]
tCY vs VDD (Operating on Main System Clock)
70 64 30 6 5 4 3
Guaranteed Operation Range
2
1
0.5 0 1 2 3 4 5 6
Supply Voltage VDD [V]
56
PD75304B,75306B,75308B
SERIAL TRANSFER OPERATION 2-Wired and 3-Wired Serial I/O Mode (SCK ... Internal clock output): (Ta = -40 to +85 C, VDD = 2.0 to 6.0 V)
PARAMETER
SYMBOL
TEST CONDITIONS VDD = 4.5 to 6.0 V
MIN. 1600 3800
TYP.
MAX.
UNIT ns ns ns ns ns
SCK cycle time
tKCY1
SCK width high/ low SI setup time (to SCK ) SI hold time (from SCK ) SO output delay time from SCK
tKL1 tKH1
VDD = 4.5 to 6.0 V
tKCY1/2-50 tKCY1/2-150 250
tSIK1
tKSI1 VDD = 4.5 to 6.0 V
400 250 1000
ns ns ns
tKSO1
RL = 1 k, CL = 100 pF*
2-Wired and 3-Wired Serial I/O Mode (SCK ... External clock input): (Ta = -40 to +85 C, VDD = 2.0 to 6.0 V)
PARAMETER SYMBOL TEST CONDITIONS VDD = 4.5 to 6.0 V SCK cycle time tKCY2 3200 SCK width high/ low SI setup time (to SCK) SI hold time (from SCK) SO output delay time from SCK tKL2 tKH2 VDD = 4.5 to 6.0 V 400 1600 100 ns ns ns ns MIN. 800 TYP. MAX. UNIT ns
tSIK2
tKSI2 VDD = 4.5 to 6.0 V
400 300 1000
ns ns ns
tKSO2
RL = 1 k, CL = 100 pF*
*
RL and CL are load resistor and load capacitance of the SO output line.
57
PD75304B,75306B,75308B
SBI Mode (SCK ... Internal clock output (Master)): (Ta = -40 to +85 C, VDD = 2.0 to 6.0 V)
PARAMETER SYMBOL TEST CONDITIONS VDD = 4.5 to 6.0 V SCK cycle time tKCY3 3800 SCK width high/ low SB0, 1 setup time (to SCK) SB0, 1 hold time (from SCK) SB0, 1 output delay time from SCK SB0, 1 from SCK SCK from SB0, 1 SB0, 1 width low SB0, 1 width high tKL3 tKH3 VDD = 4.5 to 6.0 V tKCY3/2-50 tKCY3/2-150 250 ns ns ns ns MIN. 1600 TYP. MAX. UNIT ns
tSIK3
tKSI3 VDD = 4.5 to 6.0 V
tKCY3/2 0 0 tKCY3 tKCY3 tKCY3 tKCY3 250 1000
ns ns ns ns ns ns ns
tKSO3
RL = 1 k, CL = 100 pF*
tKSB tSBK tSBL tSBH
SBI Mode (SCK ... External clock input (Slave)): (Ta = -40 to +85 C, VDD = 2.0 to 6.0 V)
PARAMETER SCK cycle time SYMBOL TEST CONDITIONS VDD = 4.5 to 6.0 V tKCY4 3200 SCK width high/ low SB0, 1 setup time (to SCK ) SB0, 1 hold time (from SCK ) SB0, 1 output delay time from SCK SB0, 1 from SCK SCK from SB0, 1 SB0, 1 width low SB0, 1 width high tKL4 tKH4 VDD = 4.5 to 6.0 V 400 1600 100 ns ns ns ns MIN. 800 TYP. MAX. UNIT ns
tSIK4
tKSI4 VDD = 4.5 to 6.0 V
tKCY4/2 0 0 tKCY4 tKCY4 tKCY4 tKCY4 300 1000
ns ns ns ns ns ns ns
tKSO4
RL = 1 k, CL = 100 pF*
tKSB tSBK tSBL tSBH
*
RL and CL are load resistor and load capacitance of the SB0, 1 output lines.
58
PD75304B,75306B,75308B
AC Timing Test Point (Excluding X1 and XT1 inputs)
0.8 VDD 0.2 VDD
Test Points
0.8 VDD 0.2 VDD
Clock Timings
1/fX tXL tXH
X1 Input
VDD -0.5 V 0.4 V
1/fXT tXTL tXTH
XT1 Input
VDD -0.5 V 0.4 V
TI0 Timing
1/fTI tTIL tTIH
TI0
59
PD75304B,75306B,75308B
Serial Transfer Timing 3-wired serial I/O mode:
tKCY1 tKL1 tKH1
SCK
tSIK1
tKSI1
SI tKSO1
Input Data
SO
Output Data
2-wired serial I/O mode:
tKCY2 tKL2 tKH2
SCK tSIK2
tKSI2
SB0,1
tKSO2
60
PD75304B,75306B,75308B
Serial Transfer Timing Bus release signal transfer:
tKL3,4 tKCY3,4 tKH3,4
SCK tSIK3,4
tKSB
tSBL
tSBH
tSBK
tKSI3,4
SB0,1
tKSO3,4
Command signal transfer:
tKCY3,4 tKH3,4
tKL3,4
SCK tSIK3,4
tKSB
tSBK
tKSI3,4
SB0,1 tKSO3,4
Interrupt Input Timing
tINTL
tINTH
INT0,1,2,4 KR0-7
RESET Input Timing
tRSL
RESET
61
PD75304B,75306B,75308B
DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (Ta = -40 to 85 C)
PARAMETER Data retention supply voltage Data retention supply current*1 Release signal setup time Oscillation stabilization wait time*2 SYMBOL VDDDR IDDDR tSREL Release by RESET tWAIT Release by interrupt request *3 ms VDDDR = 2.0 V 0 217/fx TEST CONDITIONS MIN. 2.0 0.3 TYP. MAX. 6.0 15 UNIT V
A s
ms
*
1. Current which flows in the on-chip pull-up resistor is not included. 2. The oscillation stabilization wait time is the time during which the CPU operation is stopped to prevent unstable operation at the oscillation start. 3. Depends on the basic interval timer mode register (BTM) setting (table below).
BTM3 -- -- -- --
BTM2 0 0 1 1
BTM1 0 1 0 1
BTM0 0 1 1 1
WAIT TIME (Figures in parentheses are for operation at fx = 4.19 MHz) 220/fx (approx. 250 ms) 217/fx (approx. 31.3 ms) 215/fx (approx. 7.82 ms) 213/fx (approx. 1.95 ms)
62
PD75304B,75306B,75308B
Data Retention Timing (STOP mode release by RESET)
Internal Reset Operation HALT Mode STOP Mode Data Retention Mode Operating Mode
VDD VDDDR STOP Instruction Execution tSREL
RESET
tWAIT
Data Retention Timing (Standby release signal: STOP mode release by interrupt signal)
HALT Mode STOP Mode Data Retention Mode Operating Mode
VDD VDDDR STOP Instruction Execution tSREL
Standby Release Signal (Interrupt Request) tWAIT
63
PD75304B,75306B,75308B
12. PACKAGE INFORMATION
80 PIN PLASTIC QFP ( 14)
A B
60 61
41 40 detail of lead end
D
C
S
80 1
21 20
F
G
H
IM
J
K P
N
L S80GC-65-3B9-3
NOTE Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition.
ITEM A B C D F G H I J K L M N P Q S
MILLIMETERS 17.2 0.4 14.0 0.2 14.0 0.2 17.2 0.4 0.8 0.8 0.30 0.10 0.13 0.65 (T.P.) 1.6 0.2 0.8 0.2 0.15+0.10 -0.05 0.10 2.7 0.1 0.1 3.0 MAX.
M
INCHES 0.677 0.016 0.551+0.009 -0.008 0.551+0.009 -0.008 0.677 0.016 0.031 0.031 0.012+0.004 -0.005 0.005 0.026 (T.P.) 0.063 0.008 0.031+0.009 -0.008 0.006+0.004 -0.003 0.004 0.106 0.004 0.004 0.119 MAX.
64
55
Q
PD75304B,75306B,75308B
80 PIN PLASTIC QFP (14x20)
A B
64 65
41 40 detail of lead end
D
C
S
80 1
25 24
F
G
H
IM
J K
P
N NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition.
L P80GF-80-3B9-2 ITEM A B C D F G H I J K L M N P Q S MILLIMETERS 23.6 0.4 20.0 0.2 14.0 0.2 17.6 0.4 1.0 0.8 0.35 0.10 0.15 0.8 (T.P.) 1.8 0.2 0.8 0.2 0.15+0.10 -0.05 0.15 2.7 0.1 0.1 3.0 MAX. INCHES 0.929 0.016 0.795 +0.009 -0.008 0.551+0.009 -0.008 0.693 0.016 0.039 0.031 0.014 +0.004 -0.005 0.006 0.031 (T.P.) 0.071 -0.009 0.031+0.009 -0.008 0.006+0.004 -0.003 0.006 0.106 0.004 0.004 0.119 MAX.
+0.008
M
55
Q
65
PD75304B,75306B,75308B
80 PIN PLASTIC TQFP (FINE PITCH) (
A B
12)
60 61
41 40
detail of lead end
C
D
S Q
80
21 1 20
F
G
H
I
M
J
K
P
N L
NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition.
ITEM MILLIMETERS A B C D F G H I J K L M N P Q R S 14.00.2 12.00.2 12.00.2 14.00.2 1.25 1.25 0.22 +0.05 -0.04 0.10 0.5 (T.P.) 1.00.2 0.50.2 INCHES 0.551 +0.009 -0.008 0.472 +0.009 -0.008 0.472 +0.009 -0.008 0.551 +0.009 -0.008 0.049 0.049 0.0090.002 0.004 0.020 (T.P.) 0.039 +0.009 -0.008 0.020 +0.008 -0.009
M
0.145 +0.055 0.0060.002 -0.045 0.10 1.05 0.050.05 55 1.27 MAX. 0.004 0.041 0.0020.002 55 0.050 MAX. P80GK-50-BE9-4
66
R
PD75304B,75306B,75308B
13. RECOMMENDED SOLDERING CONDITIONS
These products should be soldered and mounted under the conditions recommended below. For details of recommended soldering conditions, refer to the information document "Surface Mount Technology Manual (IEI 1207)". For soldering methods and conditions other than those recommended, please contact our salesman. Table 13-1 Surface Mount Type Soldering Conditions (1) PD75304BGC-xxx-3B9: 80-Pin Plastic QFP (s 14 mm) s PD75306BGC-xxx-3B9: 80-Pin Plastic QFP (s 14 mm) s PD75308BGC-xxx-3B9: 80-Pin Plastic QFP (s 14 mm) s
Soldering Method Soldering ConditionsRecommended Package peak temperature: 230C Duration: 30 sec. max. (210C or above) Number of applications: one Time limit: 7 days* (thereafter 20 hours 125C prebaking required) Package peak temperature: 215C Duration: 40 sec. max. (200C or above) Number of applications: one Time limit: 7 days* (thereafter 20 hours 125C prebaking required) Pin part temperature: 300C or less Duration: 3 sec. max. (per side of device) Condition Symbol
5
Infrared reflow
IR30-207-1
VPS
VP15-207-1
Pin part heating
(2) PD75304BGF-xxx-3B9: 80-Pin Plastic QFP (14 x 20 mm) PD75306BGF-xxx-3B9: 80-Pin Plastic QFP (14 x 20 mm) PD75308BGF-xxx-3B9: 80-Pin Plastic QFP (14 x 20 mm)
Soldering Method Infrared reflow Soldering ConditionsRecommended Package peak temperature: 230C Duration: 30 sec. max. (210C or above) Number of applications: one Package peak temperature: 215C Duration: 40 sec. max. (200C or above) Number of applications: one Solder bath temperature: 260C or less Duration: 10 sec. max. Number of applications: one Preparatory heating temperature: 120C max. (package surface temperature) Pin part temperature: 300C or less Duration: 3 sec. max. (per side of device) Condition Symbol IR30-00-1 VP15-00-1
VPS
Wave soldering
WS60-00-1
Pin part heating
*
For the storage period after dry-pack decapsulation, storage conditions are max. 25C, 65% RH. Use of more than one soldering method should be avoided (except in the case of pin part heating).
Note
67
PD75304B,75306B,75308B
(3) PD75304BGK-xxx-3B9: 80-Pin Plastic TQFP (s 12 mm) s PD75306BGK-xxx-3B9: 80-Pin Plastic TQFP (s 12 mm) s PD75308BGK-xxx-3B9: 80-Pin Plastic TQFP (s 12 mm) s
Soldering Method Soldering ConditionsRecommended Package peak temperature: 230C Duration: 30 sec. max. (210C or above) Number of applications: one Time limit: 1 day* (thereafter 16 hours 125C prebaking required) Package peak temperature: 215C Duration: 40 sec. max. (200C or above) Number of applications: one Time limit: 1 day* (thereafter 16 hours 125C prebaking required) Pin part temperature: 300C or less Duration: 3 sec. max. (per side of device) Condition Symbol
Infrared reflow
IR30-161-1
VPS
VP15-161-1
Pin part heating
*
For the storage period after dry-pack decapsulation, storage conditions are max. 25C, 65% RH. Use of more than one soldering method should be avoided (except in the case of pin part heating).
Note
NOTICE Recommended soldering conditions have been improved for some of these products. (Improvements: Relaxation of infrared reflow peak temperature (235C, number of applications (two), time limit, etc.) Please contact your NEC sales representative for details.
68
PD75304B,75306B,75308B
[MEMO]
69
PD75304B,75306B,75308B
5 APPENDIX A. DIFFERENCES AMONG SERIES PRODUCTS
Product Name Item Supply voltage range ROM configuration Program memory (bytes) Data memory (x 4 bits) Instruction cycle
PD75304/75306/75308
PD75312/75316
PD75P308
5V5% EPROM/Onetime
PD75P316
2.0 to 6.0 V
Mask ROM 4096/6016/8064 12160/16256 512
One-time PROM 16256
8064
0.95 s, 1.91 s, 15.3 s (main system clock: 4.19 MHz operation) 122 s (subsystem clock: 32.768 kHz operation) 8 Pull-up resistor incorporation spesifiable by software: 23 16 40 8 Used with segment pin 10 V withstand voltage. Pull-up resistor incorporation spesifiable by mask option 10 V withstand voltage. Pull-up resistor incorporation spesifiable by mask option. (without pull-up resistor)
CMOS input CMOS input/output Input/output ports CMOS output N-ch open-drain input/output
8
* Common output: Static - 1/4 duty selected * Segment output: Max. 32 LCD controller/driver LCD drive split resistor can be incorporated by mask option. 2.0 to VDD * 8-bit timer/event counter * 8-bit basic interval timer * Watch timer * NEC standard serial bus interface (SBI) * Clock synchronous serial interface * External: 3 * Internal: 3 * External: 1 * Internal: 1 No LCD drive split resistor.
LCD drive voltage
Timer/counter
Serial interface
Vectored interrupt
Test input
Clock output (PCL) Buzzer output (BUZ)
, 524 kHz, 262 kHz, 65.5 kHz (main system clock: 4.19 MHz operation)
2 kHz (Main system clock: in 4.19 MHz operation or subsystem clock: in 32.768 kHz operation) 80-pin plastic QFP (14 x 20 mm) 80-pin plastic QFP 80-pin ceramic (14 x 20 mm) WQFN (LCC with window)
Package
80-pin plastic QFP (14 x 20 mm)
On-chip PROM product
PD75P308
PD75P316 PD75P316A
70
PD75304B,75306B,75308B
Product Name Item Supply voltage range ROM configuration Program memory (bytes) Data memory (x 4 bits) Instruction cycle
PD75304B/75306B/75308B
PD75312B
PD75316B
PD75P316B*
PD75P316A
2.0 to 6.0 V One-time PROM 16256 1024 EPROM/Onetime
Mask ROM 4096/6016/8064 512 12160
0.95 s, 1.91 s, 15.3 s (main system clock: 4.19 MHz operation) 122 s (subsystem clock: 32.768 kHz operation) 8 Pull-up resistor incorporation spesifiable by software: 23 16 40 8 Used with segment pin 10 V withstand voltage. Pullup resistor incorporation spesifiable by mask option 10 V withstand voltage. Pull-up resistor incorporation spesifiable by mask option. (without pull-up resistor)
CMOS input CMOS input/output Input/output ports CMOS output N-ch open-drain input/output
8
* Common output: Static - 1/4 duty selected * Segment output: Max. 32 LCD controller/driver LCD drive split resistor can be incorporated by mask option. LCD drive voltage * 8-bit timer/event counter * 8-bit basic interval timer * Watch timer * NEC standard serial bus interface (SBI) * Clock synchronous serial interface * External: 3 * Internal: 3 * External: 1 * Internal: 1 2.0 to VDD No LCD drive split resistor.
Timer/counter
Serial interface
Vectored interrupt
Test input
Clock output (PCL) Buzzer output (BUZ)
, 524 kHz, 262 kHz, 65.5 kHz (main system clock: 4.19 MHz operation)
2 kHz (Main system clock: in 4.19 MHz operation or subsystem clock: in 32.768 kHz operation) 80-pin ceramic WQFN 80-pin plastic QFP (14 x 20 mm)
Package
80-pin plastic QFP * (14 x 20 mm) * (s 14mm) s 80-pin plastic TQFP(s 12mm) s GF package: PD75P316A GC/GK package: PD75P316B
80-pin plastic QFP (s 14mm) s 80-pin plastic TQFP(s 12mm) s
On-chip PROM product
PD75P316B
*
Under development 71
PD75304B,75306B,75308B
APPENDIX B. DEVELOPMENT TOOLS
The following development tools are available for system development using the PD75304B/75306B/ 75308B.
IE-75000-R*1 IE-75001-R IE-75000-R-EM*2 EP-75308GF-R EV-9200G-80 EP-75308BGC-R EV-9200GC-80 Hardware EP-75308BGK-R EV-9500GK-80 PG-1500 PA-75P308GF
75X series in-circuit emulator Emulation board for the IE-75000-R or IE-75001-R Emulation probe for the PD75304BGF, 75306BGF and 75308BGF. An 80-pin conversion socket (EV-9200G-80) is also provided. Emulation probe for the PD75304BGC, 75306BGC and 75308BGC. An 80-pin conversion socket (EV-9200GC-80) is also provided. Emulation probe for the PD75304BGK, 75306BGK and 75308BGK. An 80-pin conversion adapter (EV-9200GK-80) is also provided. PROM programmer PROM programmer adapter for the PD75P316AGF, connected to the PG-1500. PROM programmer adapter for the PD75P316BGC, connected to the PG-1500. PROM programmer adapter for the PD75P316BGK, connected to the PG-1500. Host machines PC-9800 series (MS-DOSTM Ver. 3.30 to Ver. 5.00A*3) IBM PC/ATTM(PC DOSTM Ver. 3.1)
PA-75P316BGC PA-75P316BGK Software IE Control Program PG-1500 Controller RA75X Relocatable Assembler
*
1. Maintenance product 2. Not incorporated in the IE-75001-R. 3. A task swapping function is provided in Ver. 5.00/5.00A, but this function cannot be used with this software. Please refer to the 75X Series Selection Guide (IF-151) for third party development tools.
Remarks
72
PD75304B,75306B,75308B
APPENDIX C. RELATED DOCUMENTS
Device Related Documents
Document Name User's Manual Instruction Application Table Application Note 75X Series Selection Guide Document Number IEM-5016 IEM-994 IEM-5035 IEM-5041 IF-151
Development Tools Documents
Document Name IE-75000-R/IE-75001-R User's Manual Hardware IE-75000-R-EM User's Manual EP-75308GF-R User's Manual EP-75308BGC-R User's Manual EP-75308BGK-R User's Manual PG-1500 User's Manual Software RA75X Assembler Package User's Manual PG-1500 Controller User's Manual Operation Language Document Number EEU-846 EEU-673 EEU-689 EEU-825 EEU-838 EEU-651 EEU-731 EEU-730 EEU-704
Other Documents
Document Name Package Manual Surface Mount Technology Manual Quality Grande on NEC Semiconductor Device NEC Semiconductor Device Reliability & Quality Control Electrostatic Discharge(ESD) Test Semiconductor Devices Quality Guarantee Guide Microcomputer Related Products Guide Other Manufacturers Volume Document Number IEI-635 IEI-1207 IEI-1209 IEM-5068 MEM-539 MEI-603 MEI-604
*
The contents of the above related documents are subject to change without notice. The latest documents should be used for design, etc.
73
PD75304B,75306B,75308B
[MEMO]
74
PD75304B,75306B,75308B
75
PD75304B,75306B,75308B
[MEMO]
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact our sales people in advance. Application examples recommended by NEC Corporation Standard : Special : Computer, Office equipment, Communication equipment, Test and Measurement equipment, Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc. Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime systems, etc.
M4 92.6
MS-DOS is a trademark of MicroSoft Corporation. PC DOS, PC/AT is a trademark of IBM Corporation.

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